1. Field of the Invention
The present invention relates to a direct memory access control device in a multiprocessor system and a method therefor, and particularly to a structure of a direct memory access control device which enables direct transfer of data between digital data processors in a multiprocessor system, thereby improving a throughput of the multiprocessor system.
2. Description of the Background Art
In a field of digital data processing such as scientific calculation, image processing or the like, a multiprocessor system is employed for fast processing of a large volume of data by parallel operation of a plurality of processors, as disclosed in the article of "A 50 ns DSP with Parallel Processing Architecture", by K. Kaneko et al., 1987 IEEE ISSCC Digest of Technical Papers, February 1987, pp. 158 to 159. In general, a signal processor employed in such a multiprocessor system can operate both in direct memory access mode and in register transfer mode for data transfer from/to an externally provided device. In direct memory accessing mode, data transfer between a processor and an external device (a memory or processor) is effected directly under control of a direct memory access controller which is an on-chip or off-chip device. In register transfer mode, data are transferred between a processor and an external device through on-chip register or registers under control of a central processing unit CPU included in the processor. In the register transfer mode, writing data into the register, reading out data from the register to transfer the read-out data to the external device or to a predetermined internal memory and addressing for the writing and reading of data are controlled by CPU, and therefore this mode (register transfer mode) requires more time for data transfer than in DMA (direct memory access) mode. For example, in the register transfer mode, the following instructions should be executed for data transfer:
LD A, (300H) PA1 OUT (20H), A.
These two instructions require a total of 7 machine cycles. Here, the first instruction means loading of the content in the address 300H into the input/output register A, and the second instruction means outputting of the content in the register A to a device having the address (20H).
In a multiprocessor system, respective processors have different operations assigned thereto, required data are transferred between processors. For example, calculation of Y=(A+B).times.C is now considered. A first processor performs calculation of Z=(A+B), and a second processor performs calculation of Y=Z.times.C, and an external memory provided common to the first and second processors stores data of A, B and C. In such configuration, data should be transferred in DMA mode for fast calculation. Further, it is desired that a multiprocessor system should be implemented with a plurality of digital data processors of low cost and high operability from the viewpoint of system performance and system size. In the following such multiprocessor system will be described.
The multiprocessor system includes a plurality of digital data processors and an external common memory connected through a common data bus to those digital data processors. In order to access the external common memory, the respective digital data processors transfer data directly between an internal memory contained in each digital data processor and the external common memory according to a method called direct memory access. In the following, the direct memory access system in a conventional multiprocessor system will be described with reference to the drawings.
FIG. 1 shows a schematic construction of a conventional multiprocessor system. Referring to FIG. 1, the multiprocessor system shown as an example comprises three digital data processors 500a, 500b and 500c, and an external memory 503 provided in common for those digital data processors. The digital data processors 500a to 500c comprise internal data memories 501a to 501c, respectively, for storing data necessary for various operation processing, and direct memory access control devices 502a to 502c, respectively, for controlling transfer of data between the respective internal data memories 501a to 501c and the external memory 503. The respective direct memory access control devices 502a to 502c can access the internal memory 503 through an address bus 504 and a data bus 505. Address data for designating an address to be accessed in the external memory 503 is transferred onto the address bus 504. Information data transferred between the external memory and the internal data memories 501a to 501c is transmitted onto the data bus 505.
FIG. 2 is a diagram schematically showing a construction of a conventional digital data processor. Referring to FIG. 2, the conventional digital data processor comprises: an internal data memory 501, a direct memory access control device (DMAC) 502, a sequencer 506 for monitoring and controlling operation in the digital data processor 500, a processing unit 507 for performing various operation processing under the control of the sequencer 506, and an input/output interface circuit 508 for providing interface between the internal data memory 501 and the external memory 3. An internal data bus 509 for transmitting internal data and an internal address bus 510 for transmitting an internal memory address and an external memory address are provided between the input/output interface circuit 508 and the internal data memory 501. The processing unit 507 accesses the internal data memory 501 through the internal data bus 509 and the internal address bus 510.
The sequencer 506 monitors a signal state on the control bus 513 and observes whether direct memory access is enabled or not, and at the same time it controls the direct memory access control device 502 so that the digital data processor 500 carries out direct memory access operation.
The direct memory access control device 502 controls operation of the internal data memory 501 through the DMA memory control line 511 and transmits addresses for the internal memory 501 and the external memory 503 onto the internal address bus 510. Referring now to FIGS. 1 and 2, direct memory access operation in the conventional multiprocessor system will be described.
First, direct memory access operation between the internal data memory 501 and the external memory 503 (an external mode) will be described with reference to FIG. 3. Now, let us assume a case in which accessing is effected from the digital processor 500a to the external memory 503. If it becomes necessary to access the external memory 503 during execution of a given program, the sequencer 506 monitors a bus request BUSREQ and a bus acceptance signal BUSACK on the control bus 513 and determines whether access to the external memory 503 is permitted or not (S1). If there is no bus request signal BUSREQ asserted on the control bus 513, the sequencer 506 transmits a bus request signal BUSREQ requesting use of the bus and starts a direct access mode (S2). Subsequently, the sequencer 506 applies a direct memory access request signal DMARQ to the direct memory access control device 502 (S3) and when it receives a direct memory access acceptance signal DMACK from the direct memory access control device 502, it separates the processing unit 507 from the internal data memory 501 and submits, to the direct memory access control device, the transfer of data between the internal data memory 501 and the external memory 503. The direct memory access control device 502 transmits the direct memory access acceptance signal DMACK and then controls operation (write/read) of the internal data memory 501 through the DMA memory control line 511 and transmits an internal address indicating a data storing position for the internal data memory 502 and an address indicating an access position for the external memory 503 onto the internal address bus 510. The address for the external memory 503 transmitted onto the internal bus 510 is transmitted to the address bus 504 through the input/output interface circuit 508 and supplied to the external memory 503. Subsequently, transfer of data is effected between the designated address of the external memory 503 and the designated address of the internal data memory 501 through the data buses 505 and 509 and the input/output interface circuit 508 (S5). After the necessary number of transfers of data have been effected (S6), the direct memory access control device 502 is disabled under the control of the sequencer 506 and processing operation according to a program stored in advance is carried out by using data stored in the internal data memory 501 under the control of the sequencer 506.
Next, data transfer operation (a local mode) from the digital data processor 500a to the digital data processor 500b shown in FIG. 1 will be described, with reference to FIG. 4.
First, the sequencer 506 in the digital data processor 500a monitors a signal state on the control bus 513 and determines whether direct memory access is permitted or not (S10). If it is determined that direct memory access is permitted, a bus request signal BUSREQ is transmitted to the control bus 513 and the direct memory access control device 502 is activated by the above described direct memory access operation, whereby the internal data memory 501 is accessed under the control of the direct memory access control device 502a. More specifically, the direct memory access control device 502a outputs a read-out address of the internal data memory 501a onto the internal address bus 510 and transmits the data read out from the internal data memory 501a onto the internal data bus 509 according to that address. Meanwhile, the direct memory access control device generates and outputs a write-in address of the external memory 503 onto the internal address bus 510. By this sequential operation, necessary data of the internal data memory 501a is transferred to the external memory 503 through the input/output interface circuit 508 (S11). When the data transfer operation from the digital data processor 500a to the external memory 503 is terminated, the direct memory access operation of the digital data processor 500a is terminated and then direct memory access memory operation in the digital data processor 500b is started (S12). More specifically, in the digital data processor 500b, the direct memory access control device 502 in the external digital data processor 500b is activated under the control of the sequencer 506 and, in the same manner as in the above described operation of the digital data processor 500a (S13), the data written previously in the external memory 503 is transferred to the internal data memory in the digital data processor (S14).
During the data transfer operation between the digital data processor 500a and the digital data processor 500b, the bus request signal BUSREQ is transmitted on the control bus 513 and even if it becomes necessary for the third digital data processor 500c to access the external memory 503, the digital processor 500c is brought into a waiting state until the data transfer between the digital data processors 500a and 500b is terminated since the address bus 504 and the data bus 505 are being used. After the data transfer between the digital data processors 500a and 500b is terminated and the address bus 504 and the data bus 505 are released, the digital data processor 500c starts transfer of data to the external memory 503.
If data in the internal memory 501a in the digital data processor 500a is required by other digital data processors 500b and 500c, the data is first transferred from the internal data memory 501a to the external memory 503 and then is transferred from the external memory 503 to the internal data memory 501b. After the transfer of the data into the internal data memory 501b is terminated, the data is transferred from the external memory 503 to the internal memory 501c.
As described above, in the digital data processor containing the conventional direct memory access control device, direct transfer of data is effected only between the external memory 503 and the internal data memory 501. Accordingly, if a multiprocessor system is structured by using such digital data processors, transfer of data between the digital data processors needs to be effected through a low-speed external memory. Thus, the advantage of high speed in the direct memory access cannot be sufficiently utilized and data cannot be transferred at high speed between processors.
In addition, since the data bus is used in common for the plurality of digital data processors, the digital data processors not actually related with communication (transfer of data) between processors by direct memory access in the system are not permitted to access the external memory 503 during the communication between the processors. Consequently, necessary processing cannot be effected at high speed and the throughput of the whole system is lowered.
In addition, if an arbitrary digital data processor is used as a transmission source and the other digital data processors in the system are used as reception destinations to transfer data, it is necessary to use a sequence of transferring data from the transmission source to the external data memory 503 and accessing the external data memory successively by the designated digital data processors as the reception destinations. Thus, much time is required for the transfer of data to prolong the data processing time, and the thruput of the system is lowered.